A method of maintaining, as well as increasing, storage node size in densely packed memory devices is through the use of "stacked storage cell" design. With this technology, layers of a conductive material such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer with dielectric layers sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with inter-plate insulative layers having a high dielectric constant.
Conventionally, DRAMs having three-dimensional stacked capacitor cells use metal oxide semiconductor field effect transistor (MOSFET) as a storage node access transistor and are processed in such a way that the transistor's source/drain diffusion regions are doped via a heavily implant prior to the formation of digitlines. If the digitlines are polysilicon or polycided materials then usually the formation of digitlines are formed after the channel transistor source/drain diffusion implant but before storage poly and cell-plate poly formation. On the other hand, if the digitlines are metal such as aluminum material, the digitlines are normally formed after storage poly and cell-plate poly formations.
As DRAM density increases (16MBit and beyond) the minimum feature size spacing will make it difficult to handle many isotropic oxide depositions without suffering from oxide buildup or oxide gap bridging problems. For example, in 16MBit stacked capacitor DRAMs, an access N-channel transistor gate wordline spacing for poly digitline buried contact is usually around the minimum feature size. The spacing has to handle at least two major isotropic silicon oxide (usually TEOS) deposition steps: one oxide layer for an N-channel LDD (lightly doped drain) spacer; and another oxide layer to serve as a digitline poly etch stopper. These two oxide depositions are a must for conventional high density stacked capacitor DRAMs with LDD due to the fact that the N-channel source/drain diffusion heavy arsenic implant is carried out prior to the formation of next poly step.
The present invention develops a method of an existing stacked capacitor fabrication process that uses only one oxide layer to serve as an N-channel LDD spacer as well as a subsequent poly etch stopper.